// Copyright (C) 1953-2022 NUDT
// Verilog module name - mbus_parse_and_encapsulate_osm 
// Version: V4.1.0.20221206
// Created:
// Created:
//         by - fenglin 
////////////////////////////////////////////////////////////////////////////
// Description:
//         
///////////////////////////////////////////////////////////////////////////

`timescale 1ns / 1ps

module mbus_parse_and_encapsulate_osm
(
        i_clk              ,
        i_rst_n            ,

        iv_command        ,
        i_command_wr      ,
        ov_command_ack    , 
        o_command_ack_wr  ,

		o_slave_port                ,
        
        iv_rxasyncfifo_overflow_cnt ,
        iv_rxasyncfifo_underflow_cnt,
        iv_txasyncfifo_overflow_cnt ,
        iv_txasyncfifo_underflow_cnt
);
// I/O
// i_clk & rst
input                  i_clk;
input                  i_rst_n;

input      [63:0]      iv_command;
input                  i_command_wr;      
output reg [63:0]      ov_command_ack;  
output reg             o_command_ack_wr;

output reg             o_slave_port;
input      [15:0]      iv_rxasyncfifo_overflow_cnt;
input      [15:0]      iv_rxasyncfifo_underflow_cnt;
input      [15:0]      iv_txasyncfifo_overflow_cnt;
input      [15:0]      iv_txasyncfifo_underflow_cnt;
//***************************************************
//               command parse
//***************************************************
always @(posedge i_clk or negedge i_rst_n) begin
    if(i_rst_n == 1'b0)begin       
        ov_command_ack    <= 64'b0;
        o_command_ack_wr  <= 1'b0 ;

        o_slave_port      <= 1'b0;		
    end
    else begin
        if(i_command_wr)begin
            if(iv_command[63:62] == 2'b00)begin//write
                ov_command_ack    <= 64'b0;
                o_command_ack_wr  <= 1'b0 ;        
                if(iv_command[50:32] == 19'd0)begin
                    o_slave_port      <= iv_command[0];
                end
                else begin
                    o_slave_port      <= o_slave_port;
                end
            end
            else if(iv_command[63:62] == 2'b10)begin//read
                if(iv_command[50:32] == 19'd0)begin
                    ov_command_ack[63:62]    <= 2'b11;//read ack
                    ov_command_ack[61:58]    <= 4'b0 ; 
                    ov_command_ack[57:32]    <= iv_command[57:32];//module id and module addr
                    ov_command_ack[31:0]     <= {31'b0,o_slave_port}; 
                    o_command_ack_wr         <= 1'b1 ;  
                end	
                else if(iv_command[50:32] == 19'd1)begin
                    ov_command_ack[63:62]    <= 2'b11;//read ack
                    ov_command_ack[61:58]    <= 4'b0 ; 
                    ov_command_ack[57:32]    <= iv_command[57:32];//module id and module addr
                    ov_command_ack[31:0]     <= {iv_rxasyncfifo_underflow_cnt,iv_rxasyncfifo_overflow_cnt}; 
                    o_command_ack_wr         <= 1'b1 ; 
                end
                else if(iv_command[50:32] == 19'd2)begin
                    ov_command_ack[63:62]    <= 2'b11;//read ack
                    ov_command_ack[61:58]    <= 4'b0 ; 
                    ov_command_ack[57:32]    <= iv_command[57:32];//module id and module addr
                    ov_command_ack[31:0]     <= {iv_txasyncfifo_underflow_cnt,iv_txasyncfifo_overflow_cnt}; 
                    o_command_ack_wr         <= 1'b1 ; 
                end        
                else begin
                    ov_command_ack    <= 64'b0;
                    o_command_ack_wr  <= 1'b0 ;
                end             
            end
        end      
        else begin               
            ov_command_ack    <= 64'b0;
            o_command_ack_wr  <= 1'b0 ;   
        end
    end
end    
endmodule
    